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may 2007 rev 5 1/57 1 M41T82 m41t83 serial i 2 c bus rtc with battery switchover features 2.0v to 5.5v clock operating voltage ultra-low battery supply current of 365na counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century programmable clock calibration (analog and digital) automatic switchover and reset output circuitry (fixed reference) ?m41t83s v cc = 3.00v to 5.50v (2.85v v rst 3.00v) ?m41t83r v cc = 2.70v to 5.50v (2.55v v rst 2.70v) ?m41t83z v cc = 2.38v to 5.50v (2.25v v rst 2.38v) serial interface supports i 2 c bus (400khz protocol) programmable alarm with interrupt function (valid even during battery back-up mode) optional 2 nd programmable alarm available square wave output defaults to 32khz on power-up (m41t83 only) reset (rst ) output watchdog timer programmable 8-bit counter/timer 7 bytes of battery-backed user sram battery low flag power-down time stamp (ht bit) low operating current of 80a 1. contact local st sales office for availability of sox18 package. oscillator stop detection battery or super-cap? back-up operating temperature of ?40c to 85c package options include: ? a 16-lead qfn (m41t83), ? an 18-lead embedded crystal soic (m41t83), or ? an 8-lead soic (M41T82) rohs compliance: lead-free components are compliant with the rohs directive. sox18 (my, 18-pin, 300mil soic qfn16, 4mm x 4mm (qa) so8 (m) 1 18 with embedded crystal) 1 (vfqfpn16) www.st.com
contents M41T82 m41t83 2/57 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 data retention and battery switchover (v so = v rst ) . . . . . . . . . . . . . . . . 20 2.5 power-on reset (t rec ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 clock/control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 real time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1 digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 28 3.4.2 analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 30 3.5 setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6 optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.7 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.8 8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.8.1 timer interrupt/timer pulse (ti /tp, m41t83 only) . . . . . . . . . . . . . . . . . 38 3.8.2 timer flag (tf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.8.3 timer interrupt enable (tie, m41t83 only) . . . . . . . . . . . . . . . . . . . . . . 39 3.8.4 timer enable (te) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.8.5 td1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.9 square wave output (m41t83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.10 battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.11 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
M41T82 m41t83 contents 3/57 3.12 output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.13 oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.14 oscillator fail interrupt enable (m41t83 only) . . . . . . . . . . . . . . . . . . . . . 42 3.15 initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.16 otp bit operation (m41t83 in sox18 package only) . . . . . . . . . . . . . . . 43 4 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
list of tables M41T82 m41t83 4/57 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. M41T82 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3. key to table 2 (M41T82 clock/control register map (32 bytes)) . . . . . . . . . . . . . . . . . . . . . 24 table 4. m41t83 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5. key to table 4 (m41t83 clock/control register map (32 bytes)) . . . . . . . . . . . . . . . . . . . . . 26 table 6. digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. interrupt operation (bit ti /tp = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. timer source clock frequency selection (244.1s to 4.25 hrs) . . . . . . . . . . . . . . . . . . . . . . 39 table 12. timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 14. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 17. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 18. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 19. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 20. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 22. oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data . . . . . . . . . . . . . . . . 51 table 26. sox18 ? 18-lead plastic small outline, 300mils, embedded crystal, package mech. . . . . . 53 table 27. so8 ? 8-lead plastic small outline (150 mils body width), package mech. data . . . . . . . . . 54 table 28. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
M41T82 m41t83 list of figures 5/57 list of figures figure 1. M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. m41t83 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. so8 (m) connections (M41T82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. qfn16 (qa) connections (m41t83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. sox18 (my) connections (m41t83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. M41T82 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. M41T82 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. m41t83 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. m41t83 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 15. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 16. internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. clock accuracy vs. on-chip load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20. crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21. alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22. back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 23. measurement ac i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 24. i cc2 vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25. power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 26. bus timing requirement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 27. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline . . . . . . . . . . . 51 figure 28. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint . . . . . . 52 figure 29. 32khz crystal + qfn16 vs. vsoj20 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30. sox18 ? 18-lead plastic small outline, 300mils, embedded crystal, outline. . . . . . . . . . . . 53 figure 31. so8 ? 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
description M41T82 m41t83 6/57 1 description the m41t8x are low power serial i 2 c real time clocks with a built-in 32.768khz oscillator (external crystal-controlled for the qfn16 and so8 packages, embedded crystal for the sox18 package). eight bytes of the register map (see table 2 on page 23 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 17 bytes of the register map provide status/control of the two alarms, watchdog, 8-bit counter, and square wave functions. an additional seven bytes are made available as user sram. addresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automatically after each write or read data byte. the m41t8x has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the clock operations can be supplied by a small lithium button battery when a power failure occurs. functions available to the user include a non-volatile, time-of-day clock/calendar, two alarm interrupts, watchdog timer, programmable 8-bit counter, and square wave outputs. the eight clock address locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. the m41t83 is supplied in either a qfn16 (qa) or an sox18 (my), 300mil soic which includes an embedded 32khz crystal. the sox18 package requires only a user-supplied battery to provide non-volatile operation. the M41T82 is available only in an so8 package.
M41T82 m41t83 description 7/57 figure 1. M41T82 logic diagram 1. open drain figure 2. m41t83 logic diagram 1. for qfn16 package only. 2. defaults to 32khz on power-up. 3. open drain sda v ss v cc v bat scl ft/rst (1) xi xo ai11196 sda v cc v ss v bat scl rst (3) irq1/out/ft (3) sqw (2) irq2 (3) xi (1) xo (1) ai11195
description M41T82 m41t83 8/57 1. for so8 and qfn16 packages only. 2. defaults to 32khz on power-up. 3. for sox18 and qfn16 packages only. 4. du pin must be tied to v cc . table 1. signal names symbol description xi (1) 32khz oscillator input xo (1) 32khz oscillator output irq1 /out/ft interrupt 1/output driver/f requency test output (open drain) sqw (2) 32khz programmable square wave output rst power-on reset output (open drain) ft/rst frequency test output/power-on reset (open drain - M41T82 only) irq2 (3) interrupt for alarm 2 (open drain) sda serial data address input/output scl serial clock input v bat battery supply voltage (tie v bat to v ss if no battery is connected.) du (4) do not use v cc supply voltage v ss ground
M41T82 m41t83 description 9/57 figure 3. so8 (m) connections (M41T82) 1. open drain output figure 4. qfn16 (qa) connections (m41t83) 1. open drain output 2. defaults to 32khz on power-up. figure 5. sox18 (my) connections (m41t83) 1. nf pins must be tied to v ss . pins 2 and 3, and 16 and 17 are internally shorted together. 2. open drain output 3. do not use (must be tied to v cc ) 4. defaults to 32khz on power-up. 2 3 45 6 8 7 1 ft/rst (1) sda v bat scl v ss xo xi v cc M41T82 ai11199 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xo xi nc v ss nc nc rst (1) nc sqw (2) nc v bat v cc irq2 (1) scl sda irq1/ft/out (1) ai11197 m41t83 8 2 3 4 5 6 7 9 12 11 10 18 17 16 15 14 13 1 nf (1) du (3) sqw (4) nc rst (2) irq2 (2) scl sda v ss v bat nf (1) nc v cc m41t83 irq1/ft/out (2) nf (1) nf (1) nc nc ai11198
description M41T82 m41t83 10/57 figure 6. M41T82 block diagram 1. v rst = v so = 2.93v (s), 2.63v (r), and 2.32v (z). 2. open drain output real time clock calendar alarm1 alarm2 watchdog oscillator fail circuit output driver 8-bit counter frequency test user sram (7 bytes) rst (2) internal power sda scl v cc compare t rec timer i 2 c interface 32khz oscillator v bat crystal xi xo v rst /v so (1) ai11812 write protect v cc < v rst ft
M41T82 m41t83 description 11/57 figure 7. M41T82 hardware hookup 1. open drain output ai11813 v cc reset input serial clock line serial data line xo xi M41T82 mcu v ss v bat ft/rst (1) sda scl v cc v cc
description M41T82 m41t83 12/57 figure 8. m41t83 block diagram 1. open drain output 2. v rst = v so = 2.93v (s), 2.63v (r), and 2.32v (z). real time clock calendar alarm1 alarm2 watchdog oscillator fail circuit square wave output driver 8 bits of otp 8-bit counter frequency test user sram (7 bytes) irq1/ft/out (1) sqw irq2 (1) rst (1) internal power sqwe a1ie sda scl v cc ofie compare t rec timer i 2 c interface 32khz oscillator v bat crystal xi xo v rst /v so (2) ai11800 write protect v cc < v rst a2ie ft out tie
M41T82 m41t83 description 13/57 figure 9. m41t83 hardware hookup 1. open drain output ai11801 v cc reset input port serial clock line serial data line 32khz clkin xo xi m41t83 mcu v ss v bat irq1/ft/out (1) rst (1) irq2 (1) sqw sda scl v cc int v cc
operation M41T82 m41t83 14/57 2 operation the m41t8x clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 32 bytes contained in the device can then be accessed sequentially in the following order: 1 st byte: tenths/hundredths of a second register 2 nd byte: seconds register 3 rd byte: minutes register 4 th byte: century/hours register 5 th byte: day register 6 th byte: date register 7 th byte: month register 8 th byte: year register 9 th byte: digital calibration register 10 th byte: watchdog register 11 th - 15 th bytes: alarm 1 registers 16 th byte: flags register 17 th byte: timer value register 18 th byte: timer control register 19 th byte: analog calibration register 20 th byte: square wave register 21 st - 25 th bytes: alarm 2 registers 26 th - 32 nd bytes: user ram the m41t8x clock continually monitors v cc for an out-of-tolerance condition. should v cc fall below v rst , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at th is time to prevent erroneous data from being written to the device from an ou t-of-tolerance system. the power input will also be switched from the v cc pin to the battery when v cc falls below the battery back-up switchover voltage (v so = v rst ). at this time the clock re gisters will be maintained by the attached battery supply. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc .
M41T82 m41t83 operation 15/57 2.1 2-wire bus characteristics the bus is intended for communication between di fferent ics. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock line is high, will be inte rpreted as control signals. accordingly, the following bus conditions have been defined: 2.1.1 bus not busy both data and clock lines remain high. 2.1.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 2.1.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. 2.1.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ? transmitter, ? the receiving device that gets the message is called ? receiver. ? the device that controls the message is called ? master. ? the devices that are controlled by the master are called ? slaves. ?
operation M41T82 m41t83 16/57 2.1.5 acknowledge each byte of eight bits is followed by one ac knowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 10. serial bus data transfer sequence figure 11. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
M41T82 m41t83 operation 17/57 2.2 read mode in this mode the master reads the m41t8x slave after setting the slave address (see figure 13 on page 18 ). following the write mode control bit (r/w = 0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w = 1). at this point the master transmitter becomes the master receiver. the data byte which was addressed will be transmitted and th e master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t8x slave transmit ter will now place the da ta byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ? an+2. ? this cycle of reading consecutive addresses will continue until the mast er receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address be ing read is a clock address (00h to 07h) . the update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-1fh). note: this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the m41t8x slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 14 on page 18 ). figure 12. slave address location ai00602 r/w slave address start a 01000 11 msb lsb
operation M41T82 m41t83 18/57 figure 13. read mode sequence figure 14. alternative read mode sequence ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
M41T82 m41t83 operation 19/57 2.3 write mode in this mode the master transmitter transmits to th e m41t8x slave receiver. bus protocol is shown in figure 15 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addressed device that word address ? an ? will follow and is to be written to the on- chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the m41t8x slave receiver will send an acknowledge cl ock to the master transmit ter after it has received the slave address see figure 12 on page 17 and again after it has received the word address and each data byte. figure 15. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
operation M41T82 m41t83 20/57 2.4 data retention and battery switchover (v so = v rst ) once v cc falls below the switchover voltage (v so = v rst ), the device automatically switches over to the battery and powers down into an ultra low current mode of operation to preserve battery life. if v bat is less than, or greater than v rst , the device power is switched from v cc to v bat when v cc drops below v rst (see figure 25 on page 48 ). at this time the clock registers and user ram will be mainta ined by the attach ed battery supply. when it is powered back up, the device switches back from battery to v cc at v so + hysteresis. when v cc rises above v rst , it will recognize the inpu ts. for more information on battery storage life refer to application note an1012. 2.5 power-on reset (t rec ) the m41t8x continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst output pulls low (open drain) and remains low after power-up for t rec (210ms typical) after v cc rises above v rst (max). note: the t rec period does not affect the rtc operation. write protect only occurs when v cc is below v rst . when v cc rises above v rst , the rtc will be selectable immediately. only the rst output is affected by the t rec period. the rst pin is an open drain output and an appropriate pull-up resistor to v cc should be chosen to control the rise time.
M41T82 m41t83 clock operation 21/57 3 clock operation the m41t8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768khz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the 8-byte clock register (see table 2 on page 23 and table 4 on page 25 ) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. bit d7 of register 01h contains the stop bi t (st). setting this bit to a '1' will cause the oscillator to stop. when reset to a '0' the os cillator restarts within one second (typical). note: upon initial power-up, the user should set the st bit to a '1,' then immediately reset the st bit to '0.' this provides an additional ?kick-start? to the oscillator circuit. bits d6 and d7 of clock register 03h (century/ hours register) contain the century bit 0 (cb0) and century bit 1 (cb1). bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). for the m41t83, bit d7 of register 0 9h (watchdog register ) contains the oscillator fail interrupt enable bit (ofie). when the user sets this bit to '1,' any condition which sets the oscillator fail bit (of) (see section 3.13: o scillator fail detection on page 42 ) will also generate an interrupt output. note: a write to any location within the first eight bytes of the clock register (00h-07h), including the st bit and cb0-cb1 bits will resu lt in an update of the system clock and a reset of the divider chain. this could result in an inadvertent change of the current time. these non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a trans ition of data during the read. 3.1 power-down time-stamp when a power failure occurs, the halt update bit (ht) will automati cally be set to a ?1?. this will prevent the clock from updating the clock registers, an d will allow the user to read the exact time of the power-down event. resetting the ht bit to a ?0? will allow the clock to update the clock with the current time. for more information, see application note an1572.
clock operation M41T82 m41t83 22/57 3.2 clock/control register map the m41t8x offers 32 internal registers which contain clock, calibration (digital and analog), alarm 1 and 2, watchdog, flags, timer, and square wave (m41t83 only). the clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referr ed to as biport? timekeeper ? cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address (00h to 07h). the system-to-user tr ansfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume either due to a stop condition or when the pointer increments to a non-clock address. clock and alarm registers store data in bcd format. calibration, timer, watchdog, and square wave bits are written in a binary format.
M41T82 m41t83 clock operation 23/57 table 2. M41T82 clock/control register map (32 bytes) (1) 1. see table 3: key to table 2 (M41T82 cloc k/control register map (32 bytes)) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h cb1 cb0 10 hours hours (24 hour format) century/hours 0-3/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h 0 ft dcs dc4 dc3 dc2 dc1 dc0 digital calibration 09h 0 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah 0 0 abe al1 10m alarm1 month al1 month 01-12 0bh rpt14 rpt15 ai1 10 date alarm1 date al1 date 01-31 0ch rpt13 ht ai1 10 hour alarm1 hour al1 hour 00-23 0dh rpt12 alarm1 10 minutes alarm1 minutes al1 min 00-59 0eh rpt11 alarm1 10 seconds alarm1 seconds al1 sec 00-59 0fh wdf af1 af2 (2) 2. af2 will always read ?0?, if the al2e bit is set to ?0?. bl tf of 0 0 flags 10h timer countdown value timer value 11h te 0 0 0 0 0 td1 td0 timer control 12h acs ac6 ac5 ac4 ac3 ac2 ac1 ac0 analog calibration 13h 0 0 0 0 0 0 al2e 0 sqw 14h 0 0 0 al2 10m alarm2 month sram/al2 month 01-12 15h rpt24 rpt25 ai2 10 date alarm2 month sram/al2 date 01-31 16h rpt23 0 ai2 10 hour alarm2 date sram/al2 hour 00-23 17h rpt22 alarm2 10 minutes alarm2 minutes sram/al2 min 00-59 18h rpt21 alarm2 10 seconds alarm2 seconds sram/al2 sec 00-59 19h-1fh user sram (7 bytes) sram
clock operation M41T82 m41t83 24/57 table 3. key to table 2 (M41T82 clock/control register map (32 bytes)) code explanation 0 must be set to zero abe alarm in battery back-up enable bit ac0-ac6 analog calibration bits acs analog calibration sign bit af1, af2 alarm flag bits al2e alarm 2 enable bit bl battery low bit bmb0-bmb4 watchdog multiplier bits cb0, cb1 century bits dc0-dc4 digital calibration bits dcs digital calibration sign bit ft frequency test bit ht halt update bit of oscillator fail bit rb0-rb2 watchdog resolution bits rpt11-rpt15 alarm 1 repeat mode bits rpt21-rpt25 alarm 2 repeat mode bits st stop bit td0, td1 timer frequency bits te timer enable bit tf timer flag wdf watchdog flag
M41T82 m41t83 clock operation 25/57 table 4. m41t83 clock/control register map (32 bytes) (1) 1. see table 5: key to table 4 (m41t83 cloc k/control register map (32 bytes)) . addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h cb1 cb0 10 hours hours (24 hour format) century/hours 0-3/00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft dcs dc4 dc3 dc2 dc1 dc0 digital calibration 09h ofie bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah a1ie sqwe abe al1 10m alarm 1month al1 month 01-12 0bh rpt14 rpt15 ai1 10 date alarm1 date al1 date 01-31 0ch rpt13 ht ai1 10 hour alarm1 hour al1 hour 00-23 0dh rpt12 alarm1 10 minutes alarm1 minutes al1 min 00-59 0eh rpt11 alarm1 10 seconds alarm1 seconds al1 sec 00-59 0fh wdf af1 af2 (2) 2. af2 will always read ?0?, if the al2e bit is set to ?0?. bl tf of 0 0 flags 10h timer countdown value timer value 11h te ti /tp tie 0 0 0 td1 td0 timer control 12h acs ac6 ac5 ac4 ac3 ac2 ac1 ac0 analog calibration 13h rs3 rs2 rs1 rs0 0 0 al2e otp sqw 14h a2ie 0 0 al2 10m alarm2 month sram/al2 month 01-12 15h rpt24 rpt25 ai2 10 date alarm2 date sram/al2 date 01-31 16h rpt23 0 ai2 10 hour alarm2 hour sram/al2 hour 00-23 17h rpt22 alarm2 10 minutes alarm2 minutes sram/al2 min 00-59 18h rpt21 alarm2 10 seconds alarm2 seconds sram/al2 sec 00-59 19h- 1fh user sram (7 bytes) sram
clock operation M41T82 m41t83 26/57 table 5. key to table 4 (m41t83 clock/control register map (32 bytes)) code explanation 0 must be set to zero abe alarm in battery back-up enable bit a1ie, a2ie alarm inte rrupt enable bits ac0-ac6 analog calibration bits acs analog calibration sign bit af1, af2 alarm flag al2e alarm 2 enable bit bl battery low bit bmb0-bmb4 watchdog multiplier bits cb0, cb1 century bits dc0-dc4 digital calibration bits dcs digital calibration sign bit ft frequency test bit ht halt update bit of oscillator fail bit out output level ofie oscillator fail interrupt enable otp otp control bit rb0-rb2 watchdog resolution bits rpt11-rpt15 alarm 1 repeat mode bits rpt21-rpt25 alarm 2 repeat mode bits rs0-rs3 sqw frequency sqwe square wave enable sram/alm2 sram/alarm 2 bit st stop bit td0, td1 timer frequency bits te timer enable bit tf timer flag ti /tp timer interrupt or pulse tie timer interrupt enable wdf watchdog flag
M41T82 m41t83 clock operation 27/57 3.3 real time clock accuracy the m41t8x is driven by a quartz contro lled oscillator with a no minal frequency of 32,768hz. the accuracy of the real time clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscilla tor circuit and the capacitive load for which the crystal was trimmed. temperature also affects the crystal frequency, causing additional error (see figure 17 on page 31 ). the m41t8x provides the option of clock correction through either manufacturing calibration or in-application calibration. the total possible compensation is typically ?93 ppm to +156 ppm. the two compensation circuits that are available are: 1. an analog calibration register (12h) can be used to adjust internal (on-chip) load capacitors for oscillator capacitance tri mming. the individual load capacitors c xi and c xo (see figure 16 ), are selectable from a range of ?18pf to +9.75pf in steps of 0.25pf. this translates to a calculated co mpensation of approximately 30 ppm (see section 3.4.2: analog calibration (programmable load capacitance) on page 30 ). 2. a digital calibration register (08h) can also be used to adjust the clock counter by adding or subtracting a pulse at the 512hz divider stage. this approach provides periodic compensation of approximately ?63 ppm to +126 ppm (see section 3.4.1: digital calibration (periodic counter correction) on page 28 ). figure 16. internal load capacitance adjustment ai11804 xo xi crystal oscillator c xi c xo
clock operation M41T82 m41t83 28/57 3.4 clock calibration the m41t8x oscillator is designed for use with a 12.5pf crystal load c apacitance. when the calibration circuit is properly employed, accuracy improves to better than 1 ppm at 25c. the m41t8x design provides the following two methods for clock error correction. 3.4.1 digital calibration (p eriodic counter correction) this method employs the use of periodic counter correction by adjusting the ratio of the 100hz divider stage to the 512hz divider stage . under normal operation, the 100hz divider stage outputs precisely 100 pulses for every 512 pulses of the 512hz input stage to provide the input frequency to the fraction of seconds clock register. by adjusting the number of 512hz input pulses used to generate 100 outpu t pulses, the clock can be sped up or slowed down, as shown in figure 19 on page 34 . when a non-zero value is loaded into the fi ve calibration bits (dc4 ? dc0) found in the digital calibration register (08h) and the sign bit is ?1?, (indicating positive calibration), the 100hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. since the 100 pulses are now being output in a shorter window, this has the effect of speeding up the clock by 1/512 seconds for each second the ci rcuit is active. similarly, when the sign bit is ?0?, indicating negative calibration, the block outputs 100 pulses for every 513 input pulses. since the 100 pulses are then being output in a longer window, this has the effect of slowing down the clock by 1/512 seconds for each second the circuit is active. the amount of calibration is controlled by using the value in the calibration register (n) to generate the adjustment in one second increments. this is done for the first n seconds once every eight minutes for positive calibration, and for n seconds once every sixteen minutes for negative calibration (see table 6 on page 29 ). for example, if the calibration register is se t to '100010,' then the adjustment will occur for two seconds in every minute. similarly, if the calibration register is set to '000011,' then the adjustment will occur for 3 seconds in every alternating minute. the digital calibration bits (dc4 ? dc0) occupy the five lower order bits in the digital calibration register (08h). these bits can be set to represent any value between 0 and 31 in binary form. the sixth bit (dcs) is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within an 8-minute (positive) or 16-minute (negative) cycle. therefore, each calibration step has an effect on clock accuracy of +4.068 or ?2.034 ppm. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month, which corresponds to a total range of +5.5 or ?2.75 minutes per month. note: 1 the modified pulses are not observable on the frequency test ( ft) output, nor will the effect of the calibration be measurable real-time, due to the periodic nature of the error compensation. 2 positive digital calibration is performed on an eight minute cycle, therefore the value in the calibration register should not be modified more frequently than once every eight minutes for positive values of calibration. negative digita l calibration is performed on a sixteen minute cycle, therefore negative values in the calibration register should not be modified more frequently than once every sixteen minutes.
M41T82 m41t83 clock operation 29/57 table 6. digital calibration values calibration value (binary) calibratio n value rounded to the nearest ppm dc4 ? dc0 negative calibration (dcs = 0) positive calibration (dcs = 1) 0 (00000) 0 0 1 (00001) -2 4 2 (00010) -4 8 3 (00011) -6 12 4 (00100) -8 16 5 (00101) -10 20 6 (00110) -12 24 7 (00111) -14 28 8 (01000) -16 33 9 (01001) -18 37 10 (01010) -20 41 11 (01011) -22 45 12 (01100) -24 49 13 (01101) -26 53 14 (01110) -28 57 15 (01111) -31 61 16 (10000) -33 65 17 (10001) -35 69 18 (10010) -37 73 19 (10011) -39 77 20 (10100) -41 81 21 (10101) -43 85 22 (10110) -45 90 23 (10111) -47 94 24 (11000) -49 98 25 (11001) -51 102 26 (11010) -53 106 27 (11011) -55 110 28 (11100) -57 114 29 (11101) -59 118 30 (11110) -61 122 31 (11111) -63 126 n n/491520 (per minute) n/245760 (per minute)
clock operation M41T82 m41t83 30/57 3.4.2 analog calibration (p rogrammable lo ad capacitance) a second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. by design, the oscillator is intended to be 0 ppm crystal accuracy at room temperature (25c, see figure 17 on page 31 ). for a 12.5pf crystal, the default loading on each side of the crystal will be 25pf. for in crementing or de crementing the calibration value, capacitance will be added or removed in incremen ts of 0.25pf to each side of the crystal. internally, c load of the oscillator is changed via tw o digitally controlled capacitors, c xi and c xo , connected from the xi and xo pins to ground (see figure 16 on page 27 ). the effective on-chip series load capacitance, c load , ranges from 3.5pf to 17.4pf, with a nominal value of 12.5pf (ac0-ac6 = ?0?). the effective series load capacitance (c load ) is the combination of c xi and c xo : seven analog calibration bits, ac0 to ac6, are provided in order to adjust the on-chip load capacitance value for frequency compensation of the rtc. each bit has a different weight for capacitance adjustment. an analog calibrati on sign (acs) bit determines if capacitance is added (acs bit = ?0?, negative calibration) or removed (acs bit = ?1?, positive calibration). the majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency by removing capacitance) due to the typical characteristic of quartz crystals to slow down due to changes in temperature, but negative calibration is also available. since the analog calibration regi ster adjustment is essentially ?pulling? the fr equency of the oscillator, the resulting fre quency changes will not be linear with incremental capacitance changes. the equations which govern this mechanism indicate that smaller capacitor values of analog calibration adjustment will provide larger increments. thus, the larger values of analog calibration adjustment will produce smaller incremen tal frequency changes. these values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest capacitance settings. the range provided by the analog calibration register adjustment with a typical surface mount crystal is approximately 30 ppm around the ac6-ac0 = 0 default setting because of this property (see table7 on page31 ). c load 11c xi ? 1c xo ? + () ? =
M41T82 m41t83 clock operation 31/57 figure 17. crystal accuracy across temperature table 7. analog calibration values addr analog calibration value d7 d6 d5 d4 d3 d2 d1 d0 c xi , c xo c load (1) 1. c load = 1/(1/c xi + 1/c xo ) acs () ac6 (16pf) ac5 (8pf) ac4 (4pf) ac3 (2pf) ac2 (1pf) ac1 (0.5pf) ac0 (0.25pf) ?(c xi , c xo ) 12h 0pf x 0 0 0 0 0 0 0 25pf 12.5pf 3pf 0 0 0 0 1 1 0 0 28pf 14pf 5pf 0 0 0 1 0 1 0 0 30pf 15pf ?7pf 1 0 0 1 1 1 0 0 18pf 9pf 9.75pf (2)) 2. maximum negative calibration value 0 0 1 0 0 1 1 1 34.75pf 17.4pf ?18pf (3) 3. maximum positive calibration value 1 1 0 0 1 0 0 0 7pf 3.5pf ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k f = k x (t ? t o ) 2 f t o = 25 c 5 c
clock operation M41T82 m41t83 32/57 the on-chip capacitance can be calculated as follows: for example: c load (12h = x0000000) = 12.5pf, c load (12h =11001000) = 3.5pf, and c load (12h = 00100111) = 17.4pf. the oscillator sees a minimum of 3.5pf with no programmable load capacitance selected. note: these are typical values, and the total lo ad capacitance seen by the crystal will include approximately 1-2pf of package and board capacitance in addition to the analog calibration register value. any invalid value of analog calibration will re sult in the default capacitance of 25pf. the combination of analog and digital trimming can give up to ?93 to +156 ppm of the total adjustment. figure 18 on page 33 represents a typical curve of clock ppm adjustment versus the analog calibration value. this curve may vary with diff erent crystals, so it is good practice to evaluate the crystal to be used with an m41t8x device before establishing the adjustment values for the application in question. c load 1 2 -- - ac6 ac0 value ? decimal , () 0.25pf [] 25pf + =
M41T82 m41t83 clock operation 33/57 figure 18. clock accuracy vs. on-chip load capacitance ai13906 decreasing load cap. - 2 0 . 0 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 0 1 0 0 . 0 - 5 . 0 - 18.0- 1 5 . 0 - 1 0 . 0 0 . 0 5 . 0 9.75 a n a l o g c a l i b r a t i o n v a l u e, ac, register 0x12 p p m a d j u s t m e n t offset to c xi , c xo (pf) net equiv. load cap., c load , (pf) 10 3.5 5.0 7.5 12.5 15 17.4 0xc80xbc 0xa8 0x94 0x00 0x14 0x27 increasing load cap. slower faster xo xi crystal oscillator c xo c xi c load = c xi + c xo c xi * c xo on-chip ai13906 decreasing load cap. - 2 0 . 0 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 0 1 0 0 . 0 - 5 . 0 - 18.0- 1 5 . 0 - 1 0 . 0 0 . 0 5 . 0 9.75 a n a l o g c a l i b r a t i o n v a l u e, ac, register 0x12 p p m a d j u s t m e n t offset to c xi , c xo (pf) net equiv. load cap., c load , (pf) 10 3.5 5.0 7.5 12.5 15 17.4 0xc80xbc 0xa8 0x94 0x00 0x14 0x27 increasing load cap. slower faster xo xi crystal oscillator c xo c xi c load = c xi + c xo c xi * c xo on-chip
clock operation M41T82 m41t83 34/57 two methods are available for ascertaining how much calibration a given m41t8x may require: the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. this allows the designer to give the end us er the ability to calibrate th e clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that a ccesses either or both of the calibration bytes. the second approach is better suited to a manufacturing environment, and involves the use of the irq1 /ft/out pin. the irq1 /ft/ out pin will toggle at 512hz when ft and out bits = '1' (m41t83 only) and st = '0.' any deviation from 512hz indicates the degree and direction of oscilla tor frequency shift at the test temperature. for example, a reading of 51 2.010124hz would indicate a +20 ppm oscillator frequency error, requiring either a ?10 (xx001010) to be loaded into the digital calibration byte, or +6pf (00011000) into the analog calibration byte for correction. note: setting or changing the digital calibration byte does not affect the frequency test, square wave, or watchdog timer frequency, but changing the analog calibration byte does affect all functions derived from t he low current oscillator (see figure 19 ). figure 19. clock divider chain and calibration circuits ai11806c analog calibration circuitry remainder of divider circuit 1hz signal 512hz output frequency test 32khz low current oscillator c xi c xo 2 8 2 2 2 2 digital calibration circuitry (divide by 511/512/513) clock registers square wave watchdog timer 8-bit timer
M41T82 m41t83 clock operation 35/57 figure 20. crystal isolation example 1. substrate pad should be tied to v ss . 3.5 setting the alarm clock registers address locations 0ah-0eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings. either alarm can be configured independently to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. bits rpt15?rpt11 and rpt25-rpt21 put the alarms in the repeat mode of operation. table8 on page37 shows the possible bit configurations. codes not listed in the table default to the once-per-second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt15?rpt11 and/or rpt25-rpt21, af1 (alarm 1 flag) or af2 (alarm 2 flag) is set. if a1ie (alarm 1 interrupt enable), or a2ie (alarm 2 interrupt enable) are also set, the alarm condition activates either the irq1 /ft/out, or irq2 output pins. to disable either of the alarms, write a '0' to the alarm date registers and to the rptx5?rptx1 bits. note: if the address pointer is allowed to increment to the flag register address, or the last address written is ?alarm seconds,? the addre ss pointer will increment to the flag address, and an alarm condition will not cause the interrupt/flag to occu r until the address pointer is moved to a different address. the irq output is cleared by a read to the flags register (0fh) as shown in figure 21 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.'. ai11814 crystal xi xo v ss local grounding plane (layer 2)
clock operation M41T82 m41t83 36/57 3.6 optional second programmable alarm when the alarm 2 enable (al2e) bit (d1 of address 13h) is set to a logic ?1?, registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as the alarm function described above. the a2ie (alarm 2 interrupt enable) bit allows the second alarm to trigger a separate interrupt output (irq2 ). the al2e bit defaults on initial power-up to a logic ?0? (alarm 2 disabled). in this mode, the five address bytes (14h-18h) function as additional user sram, for a total of 12 bytes of user sram. the irq1 /ft/out pin can also be activated in the battery back-up mode (see figure 22 on page 36 ). figure 21. alarm interrupt reset waveform figure 22. back-up mode alarm waveform 1. abe and a1ie bits = 1. alarm flag bits (afx) 0fh 0eh 00h high-z ai08898 irq1/ft/out or irq2 v cc irq1/ft/out or irq2 af bit in flags register high-z v so v pfd trec ai09164c
M41T82 m41t83 clock operation 37/57 3.7 watchdog timer the watchdog timer can be used to detect an out-of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplication of the five-bit multiplier valu e with the resolution. (for example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). if the processor does not reset the timer within the specified period, the m41t8x sets the wdf (watchdog flag) and generates a watchdog interrupt. the watchdog timer can be reset by having the microprocessor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, a value of 00h needs to be written to the watchdog register in order to clear the irq1 /ft/out pin. this will also disable the watchdog function until it is again programmed correctly. a r ead of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set, the frequency test function is activated, and the sqwe bit is '0,' the watchdog function preva ils and the frequency test function is denied. table 8. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111 once per second 11110 once per minute 11100 once per hour 11000 once per day 10000 once per month 00000 once per year
clock operation M41T82 m41t83 38/57 3.8 8-bit (countdown) timer the timer value register is an 8-bit binary countdown timer. it is enabled and disabled via the timer control register (11h) te bit. other timer properties such as the source clock, or interrupt generation are also selected in the timer control register (see ta b l e 9 ). for accurate read back of the countdown value, the i 2 c-bus clock (scl) must be operating at a frequency of at least twice the selected timer clock. the timer control register selects one of four source clock frequencies for the timer (4096, 64, 1, or 1/60hz), and enables/disables the timer. the timer counts down from a software- loaded 8-bit binary value. at the end of every countdown, the timer sets the timer flag (tf) bit. the tf bit can only be cleared by software. when asserted, the timer flag (tf) can also be used to generate an interrupt (irq1 /ft/out) on the m41t83. the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of tf. the timer interrupt/timer pulse (ti /tp) bit is used to control this mode selection. when reading the timer, the current countdown value is returned. 3.8.1 timer interrupt/timer pulse (ti /tp, m41t83 only) ti /tp = 0 irq1 /ft/out is active when tf is logic '1' (subject to the status of the timer interrupt enable bit (tie). ti /tp = 1 irq1 /ft/out pulses are active when tf is logic '1' according to ta b l e 1 0 (subject to the status of the tie bit). note: if an alarm cond ition, watchdog time-out, oscilla tor failure, or out = 0 causes irq1 /ft/out to be asserted low, then irq1 /ft/out will remain asserted even if ti /tp is set to '1'. when in pulse mode (ti /tp = 1), clearing the tf bit will not stop the pulses on irq1 /ft/out. the output pulses will only stop if te, tie, or ti /tp are reset to '0'. table 9. timer control register map (1) 1. bit positions labeled with ?0? should always be written with logic '0. ' addr d7 d6 d5 d4 d3 d2 d1 d0 function 0fh wdf af1 af2 bl tf of 0 0 flags 10h timer countdown value timer value 11h te ti /tp tie 0 0 0 td1 td0 timer control
M41T82 m41t83 clock operation 39/57 3.8.2 timer flag (tf) at the end of a timer countdown, tf is set to logic '1.' if both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading the flag bits. the timer will auto-reload and continue to count down rega rdless of the state of tf bit (or ti /tp bit). the tf bit is cleared by reading the flags register. 3.8.3 timer interrupt enable (tie, m41t83 only) in level mode (ti /tp = 0), when tf is asserted, the interrupt is asserted (if tie = 1). to clear the interrupt, the tf bit or the tie bit must be reset. 3.8.4 timer enable (te) te = 0 when the timer register (10h) is set to ?0?, the timer is disabled. te = 1 the timer is enabled. te is reset (disabled) on power-down. when re-enabled, the counter will begin from the same va lue as when it was disabled. 3.8.5 td1/0 these are the timer source clock frequency selection bits (see ta bl e 1 1 ). these bits determine the source clock fo r the countdown timer (see ta bl e 1 2 ). when not in use, the td1 and td0 bits should be set to ?11? (1/60hz) for power saving. table 10. interrupt operation (bit ti /tp = 1) source clock (hz) irq (1) periods 1. tf and irq1 /ft/out become active simultaneously. n (2) = 1 2. n = loaded countdown timer value. the timer is stopped when n = 0. n > 1 4096 1/8192 1/4096 64 1/128 1/64 11/641/64 1/60 1/64 1/64 table 11. timer source clock frequency selection (244.1s to 4.25 hrs) td1 td0 timer source clock frequency (hz) 0 0 4096 (244.1s) 0 1 64 (15.6ms) 10 1 (1s) 1 1 1/60 (60s)
clock operation M41T82 m41t83 40/57 3.9 square wave output (m41t83 only) the m41t83 offers the user a programmable square wave function which is output on the sqw pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in ta bl e 1 3 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. note: if the sqwe bit is set to '1' and v cc falls below the switchover (v so ) voltage, the square wave output will be disabled. table 12. timer countdown value register bits (addr 11h) (1) 1. writing to the timer register will not reset the tf bit or clear the interrupt. bit symbol description 7 - 0 this register holds the loaded countdown value ?n?. countdown period = n / source clock frequency. table 13. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 000132.768khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
M41T82 m41t83 clock operation 41/57 3.10 battery low warning the m41t8x automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if th e battery voltage is found to be less than approximately 2.5v. the bl bit will remain assert ed until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. clock data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. however, data is not compromised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the m41t8x only monitors the battery when a nominal v cc is applied to the device. thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. 3.11 century bits these two bits will increment in a binary fashio n at the turn of the century, and handle all leap years correctly. see ta bl e 1 4 for additional explanation. 3.12 output driver pin when the ofie bit, a1ie bit, and watchdog register are not set to generate an interrupt, the irq1 /ft/out pin becomes an output driver that reflects the contents of d7 of register 08h. in other words, when d7 (out bit) is a '0,' then the irq1 /ft/out pin will be driven low. note: the irq1 /ft/out pin is an open drain which requires an external pull-up resistor. table 14. century bits examples cb0 cb1 leap year? example (1) 1. leap year occurs every four years (f or years evenly divisible by four), except for y ears evenly divisible by 100. the only exceptions are those years evenly divisible by 400 (the y ear 2000 was a leap year, year 2100 is not). 00yes2000 0 1 no 2100 1 0 no 2200 1 1 no 2300
clock operation M41T82 m41t83 42/57 3.13 oscillator fail detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time. this bit can be used to judge the validity of the clock and date data. this bit will be set to '1' any ti me the oscillator stops. in the event the of bit is found to be set to '1' at any time other than the initial power-up, the stop bit (st) should be written to a '1,' then im mediately reset to '0.' this will restart the oscillator. the following conditions can cause the of bit to be set: the first time power is applied (defaults to a '1' on power-up). note: if the of bit cannot be written to '1' 4 seconds after the initial power-up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' the voltage present on v cc or battery is insufficien t to support oscillation. the st bit is set to '1.' external interference of the crystal for the m41t83, if the oscillato r fail interrupt enable bit (o fie) is set to a '1,' the irq1 /ft/out pin will also be activated. the irq1 /ft/out output is cleared by resetting the ofie or of bit to '0' (not by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before attempting to reset the of bit to '0.' if the trigger event occurs during a power down condit ion, this bit will be set correctly. 3.14 oscillator fail interrupt enable (m41t83 only) if the oscillator fail interrupt enable bi t (ofie) is set to a '1,' the irq1 /ft/out pin will also be activated. the irq1 /ft/out output is cleared by resetting the ofie or of bit to '0' (not by reading the flags register). 3.15 initial power-on defaults upon initial application of power to the device, the register bits will initially power-on in the state indicated in ta bl e 1 5 and ta b l e 1 6 . table 15. initial power-on default values (part 1) condition (1) 1. all other control bits po wer-up in an undetermined state. st cb1 cb0 out ft dcs acs digital calib. analog calib. ofie (2) 2. m41t83 only. watchdog (3) 3. bmb0-bmb4, rb0, rb1. a1ie (2) sqwe (2) abe initial power-up 000 1 0 0 0 0 0 0 0 1 0 subsequent power-up (4) (5) 4. with battery back-up. 5. uc = unchanged. uc uc uc uc 0 uc uc uc uc 0 uc uc uc
M41T82 m41t83 clock operation 43/57 3.16 otp bit operation (m41t83 in sox18 package only) when the otp (one time programmable ) bit is set to a '1,' the value in the internal otp registers will be transferred to the analog calibration register (12h) and are ?read only.? the otp value is programmed by the manufacturer, and will contain the calibration value necessary to achieve 5 ppm at room temperature after two smt reflows. this clock accuracy can then be guaranteed to drift no more than 3 ppm the first year, and 1 ppm for each following year due to crystal aging. if the otp bit is set to '0,' the analog calibrati on register will become a wr ite/read register and function like standard sram memory cells, allowing the user to implement any desired value of analog calibration. when the user sets the otp bit, they need to wait for approximately 8ms before the analog registers transfer the value from the otp to the analog registers due to the otp read operation. table 16. initial power-up default values (part 2) condition (1) 1. all other control bits po wer-up in an undetermined state. rpt11-15 ht of te ti /tp (2) 2. m41t83 only. tie (2) td1 td0 rs0 rs1-3 otp (2) a2ie (2) rpt21- 25 al2e initial power-up 0110001110000 0 subsequent power-up (3) (4) 3. with battery back-up. 4. uc = unchanged. uc 1 uc 0 uc uc uc uc uc uc uc uc uc uc
maximum rating M41T82 m41t83 44/57 4 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 17. absolute maximum ratings sym parameter value (1) 1. data based on characterization results, not tested in production. unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 7.0 v t sld (2) 2. reflow at peak temperature of 260c (total th ermal budget not to exceed 245c for greater than 30 seconds). lead solder temperature for 10 seconds qfn16 260 c so8 sox18 245 c v io input or output volt ages ?0.2 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w
M41T82 m41t83 dc and ac parameters 45/57 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. figure 23. measurement ac i/o waveform 1. effective capacitance m easured with power supply at 3.6v ; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. table 18. operating and ac measurement conditions (1) 1. output hi-z is defined as the point where data is no longer driven. parameter m41t8x supply voltage (v cc ) 2.38v to 5.5v ambient operating temperature (t a ) ?40 to 85c load capacitance (c l ) 50pf input rise and fall times 5ns input pulse voltages 0.2v cc to 0.8 v cc input and output timing ref. voltages 0.3v cc to 0.7 v cc table 19. capacitance symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc
dc and ac parameters M41T82 m41t83 46/57 table 20. dc characteristics sym parameter test condition (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.38v to 5.5v (except where noted). min typ max unit v cc operating voltage (s) ?40 to 85c 3.00 5.50 v operating voltage (r) ?40 to 85c 2.70 5.50 v operating voltage (z) ?40 to 85c 2.38 5.50 v i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current scl = 400khz (no load) 5.5v 125 150 a 3.0v 55 a 2.5 (z only) 45 a i cc2 supply current (standby) scl = 0hz; all inputs v cc ? 0.2v or v ss + 0.2v (sqwe bit = 0) 5.5v 8 10 a 3.0v 6.5 a v il input low voltage ?0.3 0.3v cc v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage rst , ft/rst v cc /v bat = 3.0v, i ol = 1.0ma 0.4 v sqw, irq1 /ft/out v cc = 3.0v, i ol = 1.0ma 0.4 v scl, sda v cc = 3.0v, i ol = 3.0ma 0.4 v v oh output high voltage v cc = 3.0v, i oh = ?1.0ma (push-pull) 2.4 v pull-up supply voltage (open drain) irq1 /ft/out 5.5 v v bat battery back-up supply voltage (2) 2. for non-rechargeable lithium battery. 2.5 5.5 v v cap capacitor back-up supply voltage 2.0 5.5 v i bat battery supply current 25c; v cc = 0v; osc on; v bat = 3v; 32khz off 365 450 na
M41T82 m41t83 dc and ac parameters 47/57 figure 24. i cc2 vs. temperature table 21. crystal electrical characteristics symbol parameter (1) (2) 1. externally supplied if using the qfn16 or so8 pac kage. stmicroelectronics re commends the citizen cfs- 145 (1.5x5mm) and the kds dt-38 (3x8mm) for thru- hole, or the kds dmx-26s (3.2x8mm) or micro crystal ms3v-t1r (1.5x5mm) for surface-mount, tuning fork-type quartz crystals . kds can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp . citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com . micro crystal can be contacted at sales@microcrystal.ch or http://www.microcrystal.com . 2. load capacitors are integrated within the m41t8x. circ uit board layout considerations for the 32.768khz crystal of minimum trace lengths and isolation from rf generating signals should be taken into account. min typ max units f o resonant frequency 32.768 khz r s series resistance 65 (3) 3. guaranteed by design. k c l load capacitance 12.5 pf table 22. oscillator characteristics symbol parameter (1) (2) 1. with default analog calibration value ( = 0). 2. reference value. conditions min typ max units v sta oscillator start voltage 4s 2.0 v t sta oscillator start time v cc = v so 1s c xi, c xo (1) capacitor input, ca pacitor output 25 pf ic-to-ic frequency variation (2) (3) 3. t a = 25c, v cc = 5.0v. ?10 +10 ppm ai 13909 2.000 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000 -40 -20 0 20 40 60 80 temperature (?c) icc2 ( a) (3.0v) (5.0v)
dc and ac parameters M41T82 m41t83 48/57 figure 25. power down/up mode ac waveforms table 23. power down/up trip points dc characteristics sym parameter (1) (2) (1,2) 1. all voltages referenced to v ss. 2. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.38 to 5.5v (except where noted). min typ max unit v rst reset threshold voltage s 2.85 2.93 3.0 v r 2.55 2.63 2.7 v z 2.252.322.38 v v so battery back-up switchover v rst v hysteresis 25 mv t rec reset pulse width (v cc rising) 140 280 ms v cc to reset delay, v cc = (v rst + 100mv), falling to (v rst ? 100mv; for v cc slew rate of 10mv/s 2.5 s ai00596 v cc trec tpd v so sda scl don't care
M41T82 m41t83 dc and ac parameters 49/57 figure 26. bus timing requirement sequence table 24. ac characteristics sym parameter (1) 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.38 to 5.5v (except where noted). min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) 2. transmitter must internally provi de a hold time to bridge the undefined region (300ns max) of the falling edge of scl. data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s ai00589 sda p tsu:s t tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
package mechanical information M41T82 m41t83 50/57 6 package mechanical information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
M41T82 m41t83 package mechanical information 51/57 figure 27. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline 1. drawing is not to scale. table 25. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data sym mm inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.031 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 ? ? 0.008 ? ? b 0.30 0.25 0.35 0.012 0.010 0.014 d 4.00 3.90 4.10 0.157 0.154 0.161 d2 ? 2.50 2.80 ? 0.098 0.110 e 4.00 3.90 4.10 0.157 0.154 0.161 e2 ? 2.50 2.80 ? 0.098 0.110 e0.65? ?0.026? ? l 0.40 0.30 0.50 0.016 0.012 0.020 ddd ? 0.08 ? ? 0.003 ? a3 a a1 e b d2 e2 l e d 1 2 ddd 3 qfn16-a c
package mechanical information M41T82 m41t83 52/57 figure 28. qfn16 ? 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint 1. dimensions are shown in millimeters (mm). figure 29. 32khz crystal + qfn16 vs. vsoj20 mechanical data 1. dimensions shown are in millimeters (mm). 0.35 2.70 4.50 2.70 ai11815 0.65 0.70 0.325 0.20 1 16 15 14 13 xi 2 xo 3 4 ai11816 st qfn16 smt crystal vsoj2 0 3.9 3.9 1.5 3.2 6.0 0.2 7.0 0.3
M41T82 m41t83 package mechanical information 53/57 figure 30. sox18 ? 18-lead plastic small outline, 300mils, embedded crystal, outline 1. drawing is not to scale. table 26. sox18 ? 18-lead plastic small outline, 300mils, embedded crystal, package mech. symbol millimeters inches typ min max typ min max a 2.57 2.44 2.69 0.101 0.096 0.106 a1 0.23 0.15 0.31 0.009 0.006 0.012 a2 2.34 2.29 2.39 0.092 0.090 0.094 b 0.46 0.41 0.51 0.018 0.016 0.020 c 0.25 0.20 0.31 0.010 0.008 0.012 d 11.61 11.56 11.66 0.457 0.455 0.459 e 7.62 7.57 7.67 0.300 0.298 0.302 e1 10.34 10.16 10.52 0.407 0.400 0.414 e 1.27 ? ? 0.050 ? ? l 0.66 0.51 0.81 0.026 0.020 0.032 e 9 e d c h 10 18 1 b so-j a1 l a1 h x 45 a a2 ddd
package mechanical information M41T82 m41t83 54/57 figure 31. so8 ? 8-lead plastic small package outline 1. drawing is not to scale. table 27. so8 ? 8-lead plastic small outline (150 mils body width), package mech. data symb mm inches typ min max typ min max a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 - - 0.050 - - h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 0.127 0.016 0.050 l1 1.04 0.041 so-a e 8 ddd b e a d c l a1 1 h h x 45? a2 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
M41T82 m41t83 part numbering 55/57 7 part numbering for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 28. ordering information example: m41t 83 s qa 6 e device family m41t device type 82 (so8 package only) 83 operating voltage s = v cc = 3.00 to 5.5v r = v cc = 2.70 to 5.5v z = v cc = 2.38 to 5.5v package qa = qfn16 (4mm x 4mm) m (1) = so8 1. M41T82 only. my (2) = sox18 2. the sox18 package includes an embedded 32,768hz crystal. temperature range 6 = ?40c to 85c shipping method e = ecopack package, tubes f = ecopack package, tape & reel
revision history M41T82 m41t83 56/57 8 revision history date revision changes 27-jul-2006 1 first edition 17-oct-2006 2 updated package mechanical data in figure 31: so8 ? 8-lead plastic small package outline and table 27: so8 ? 8-lead plastic small outline (150 mils body width), package mech. data ; small text changes for entire document, amended footnotes in ta bl e 1 , ta bl e 1 4 and figure 5 . 19-dec-2006 3 document status upgraded to full datasheet; added footnote to diagram in features ; amended footnotes in figure 2 and updated footnotes in ta bl e 2 8 ; updated ?typical data? for i cc1 and i cc2 in ta b l e 2 0 ; updated package mechanical data for the qfn16 and sox18 in section 6 ; changed khz to khz through document; made small text changes throughout document. 08-mar-2007 4 updated cover page (features and amended footnote concerning availability), figure 18: clock accuracy vs. on-chip load capacitance , and ordering information ( ta b l e 2 8 ). 08-may-2007 5 updated title of product (added i 2 c bus) on cover page; updated section 3.16 , section 3.4.1 , ta b l e 1 7 , 20 , 28 , figure 29 ; added figure 24 ; added micro crystal information ( ta b l e 2 1 ).
M41T82 m41t83 57/57 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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